This invention pertains to Metal Oxide Silicon Field Effect Transistors (MOSFETs), and more particularly to MOSFETs which include a drain extension region which is charge-induced.
In either very short channel MOSFETs or in high voltage MOSFETs, a significant portion of the reverse biased drain-to-body junction depletion spreading and a high electric field are present under the transistor's gate region as shown in FIG. 1. Such conditions lead to premature breakdown due to field-plate induced avalanche, as shown in FIG. 1, or punch-through, as shown in FIG. 2 and described in Demoulin, E. et al., "Process Statistics of Submicron MOSFETs," IEDM 1979, paper 2.7, pp. 34-37. The high electric fields also lead to the formation and trapping of hot carriers in the gate oxide, as described in Takeda, E. et al., "Device Performance Degradation Due to Hot-Carrier Injection at Energies Below the Si-SiO.sub.2 Barrier," IEDM 1979, paper 15.5, pp. 396-399, and their associated reliability problems due to shifts in the threshold voltage. In short channel devices, charge sharing between the gate capacitor and drain-to-body junction causes a channel-length-dependent lowering of the threshold voltage as described in Shibata, T. et al., "An Optimally Designed Process for Submicron MOSFETs," IEDM 1981, pp. 647-650.
To alleviate these and related problems such as high gate-to-drain overlap capacitance, the lightly-doped-drain (LDD) MOSFET is used, as described in Ogura, S. et al., "Elimination of Hot Electron Gate Current by the Lightly Doped Drain-Source Structure," IEDM 1981, pp. 651-654. Shown in FIG. 3, LDD MOSFET 100 employs conventional heavily doped source region 101 and drain region 102 offset from polycrystalline silicon or silicide gate electrode 105 by sidewall oxide spacer 106 to which N+implants used to form source regions 101 and drain region 102 are self aligned. Such an arrangement is shown in Nakahara, M. et al., "Relief of Hot Carrier Constraint on Submicron CMOS Devices by Use of a Buried Channel Structure," IEDM 1985, pp. 238-240 Sidewall oxide spacer 106 overlays lightly doped N- source extension 103 and drain extension 104, which are created by ion implantation after formation of field oxidation 107 and gate electrode 105 but prior to formation of sidewall oxide spacer 106. Since feature sizes are small (typically around 1 .mu.m) the light ion implantation extensions and oxide spacer appears on both the drain and source side of the transistor, despite the fact that it is called a lightly-doped-drain transistor.
Lightly doped source/drain regions 103, 104 serve a number of functions. First, either one of the source/drain regions 103, 104 can, depending upon the circuit configuration, become reversed biased to body region 100, thereby serving as the drain of the device. The drain-body junction behaves as a two-sided junction in which depletion occurs on both sides of the junction, i.e. into both the drain and the body regions, reducing the amount of depletion spreading under gate electrode 105 and into channel 109. This reduction of depletion spreading under gate electrode 105 into channel 109 occurs due to the depletion spreading in the lightly doped drain region, which causes a voltage drop in the lightly doped drain. This means the amount of the source-to-drain voltage which must be sustained across the channel is reduced, thereby allowing the channel length to be decreased, and the gate oxide made thinner Second, the lightly doped source and drain extensions 103, 104 decrease the amount of hot carriers injected into gate electrode 105, thereby avoiding charge induced degradation of the transconductance (gm) of transistor 100. Lightly doped source and drain extensions 103, 104 also reduce the amount of charge sharing between the depletion region associated with the gate and the depletion region associated with the reverse biased drain-to-body diode, thus reducing channel length dependent variations of the threshold voltage of transistor 100. Extensions 103, 104 also decrease the capacitance caused by the overlap of gate 105 to the N+ source and drain diffusions 101, 102 and therefore increase the speed of transistor operation via a reduced Miller effect. The Miller effect, common to all MOSFETs, is the increase in input capacitance of a gain stage by a factor of Av*C.sub.gd, where Av is the voltage gain of the stage, and C.sub.gd is the gate-to-drain capacitance, in a conventional MOSFET the capacitance caused by the overlap of gate 105 to source and drain diffusions 101, 102. Naturally, in a MOSFET using a lightly doped drain region, C.sub.gd is the gate-to-drain overlap capacitance caused by the overlap of gate 105 to lightly doped source and drain extensions 103, 104, which is less than the C.sub.gd of a conventional MOSFET.
Lightly doped drains are used in prior art high voltage devices in order to achieve low on-resistances and high off-state blocking voltages. The technique called lateral charge control (LCC) as described in Yamaguchi, T. et al., "Process and Device Design of a 1000-Volt MOS IC," IEDM 1981, pp. 255-258, and the related technique called "reduced surface fields" (RESURF) as described in Stupp, E. et al., "Low Specific On-resistance 400V LDMOST," IEDM 1981, pp 426-428, use a drain extension which depletes when reverse biased and has been demonstrated as an effective termination (i.e. area outside of the diode which allows the radius of curvature of the diode junction to be overcome, thereby spreading out the field lines creating a lower electrical field) to over 1,000 volts. Since the feature sizes in high voltage devices are larger than those used in VLSI transistors, the lightly doped region is normally created using implant blocking masks so that a sidewall oxide spacer is not needed. In this event, the lightly doped regions are conveniently formed on only the drain side of the device.
As devices have been scaled to even smaller dimensions, the need to fabricate very shallow junctions has become increasingly important in eliminating the lateral diffusion of source and drain regions under the gate. New process techniques such as the use of slowly diffusing dopants (e.g., arsenic), shallow implants (e.g. BF.sub.2) and rapid thermal anneals of implants have been used, but often complicate or restrict the process by requiring these steps to be performed at low temperatures or for short periods of time. In high voltage transistors where a double-diffused "body" region is employed, the extra body diffusion will change the drift region dopant profile considerably unless it can be integrated into the process after the body diffusion.
Using conventional diffusion techniques as described above, the shallow lightly doped drain is achieved at the expense of a loss in flexibility in the integrated process design In cases when extremely shallow junctions are needed for high frequency or VLSI (submicron) transistors, the process may be considerably more complex than desirable. In some cases, the desired junction depth may be physically impossible using today's technology.